Nowadays, semiconductor devices are frequently used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor device widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor memory is a flash memory (e.g., a NOR flash and a NAND flash).
Memory devices such as the NOR flash and the NAND flash are typically arranged in an array of memory cells. A flash memory cell typically includes an access field effect transistor (FET) and a storage capacitor. A source/drain region of the cell access FET is coupled to a bitline, and the other source/drain region is coupled to a plate of a respective storage capacitor. The other plate of the capacitor is coupled to a common plate reference voltage. The gate of the transistor is coupled to a wordline. The storing and accessing of information into and from memory cells are achieved by selecting and applying voltages to the wordlines and bitlines.
In fabricating semiconductor devices such as flash memories, shallow trench isolation (STI) is a technique used to provide electrical isolation between various devices. In a self-aligned STI (SASTI herein after) process, wordline short caused by a polycrystalline silicon (POLY) residual after wordline etching is a frequently encountered problem. It is easy to get wordline short caused by the POLY residual and the POLY profile. The present invention is aimed at solving the short-circuit problem caused by the POLY residual and the POLY profile not only in the process for fabricating a wordline, but also in other fabricating processes involving POLY residual problems such as in a fabricating process of the NAND flash, or the NOR flash, or a POLY cell bridge.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicants finally conceived a methodology for wordline short reduction.